A logic for testing which is not utilized in the normal operating mode is increasingly important for adequate fault coverage and for reducing test costs. In the prior art, for testing an integrated circuit which is intended to be tested at various locations or which is intended to be modified relative to the normal operating mode for testing at various locations, use is usually made of a test logic which is positioned centrally or at a small number of locations on a chip of an integrated circuit. Lines have to be routed from this test logic to each location to be tested in the integrated circuits, in order to carry out functional tests there. Numerous so-called test modes are required, which have to be stored on the chip and are passed as individual signals over the chip. Test modes comprise, for example, the modification or reprogramming of voltages and the single-stage or multistage modification of the temporal control, or timing.
One disadvantage in the prior art is that the additional outlay on wiring which is required for distributing individual test modes to the be locations to be tested in the integrated circuit limits the number of possible test modes, since virtually every test mode occupies an individual wiring channel on the chip. This considerably restricts the test possibilities for an integrated circuit.
A further disadvantage in the prior art is that costly chip area is taken up by the increased outlay on wiring, which is critical in particular for cost-sensitive standard products such as e.g. dynamic random access memories (DRAM).